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Have you ever imagined of an open-source instruction set architecture (ISA) for chip designing? RISC-V is the answer.
RISC-V is a fifth generation of Reduced Instruction Set Computing architecture. RISC-V architecture follows the principle of Reduced Instruct Set computing and lays emphasis on operational efficiency, simplified chip designing, optimized software-hardware interaction and is highly energy efficient. RSIC-V provides highly customizable architecture which can be customized for designing of application specific central processing unit (CPU) or system-on-a-chip (SOC).
The founding members of RISC-V standard organisation are:
| SiFive | Codasip | IBM | Rambus |
| MIT (Csail) | Cortus | ICT | Rumble |
| Andes | Esperanto | IIT Madras | Syntacore |
| Antmicro | Espressif | Lattice | Technolution |
| Bluespec | ETH Zurich | lowRISC | |
| CEVA | Microchip |
RISC-V allows anyone to use, study, share and modify the instruction set without licensing fees or royalties. The open standard ISA encourages collaboration from various industries to academia and the development of customized processors for specific applications.
The modular design of RISV-V enables it to meet the requirements of different applications such as embedded systems, high-performance computing, and more. The enhanced customization capabilities allow developers to create application-specific processors optimized for performance and energy efficiency.
The adaptability of RISC-V makes it suitable for a wide range of sectors including telecommunications, automotive, IoT, machine learning, and more.
The lack of a licensing fee makes RISC-V an ideal option for startups, small enterprises, and big players looking to reduce operational costs. RISC-V affordability promotes innovation and allows a broad range of players to enter the market.
Following the principles of RISC, the RISC-V emphasizes simple chip design, reduces complexity, and allows for more straightforward optimization of hardware and software interactions.
| Feature | RISC | CISC |
| Instruction Set Size | Small | Large |
| Instruction Length | Short | Long |
| Execution Speed | Faster | Slower |
| Hardware Complexity | Simpler | More Complex |
| Software Development | Easier | More Difficult |
| Application | High performance computing, embedded systems | Low end and High end Computing |
RISC-V is a powerful and free open standard architecture which can be used by anyone to design, manufacture and sell application specific processors/chipsets without fear of paying for royalties. RISC-V architecture is flexible enough for selection of any of the available feature rather than compulsion to choose full set of feature.
The main moto for development of RISC-V open architecture is the need for a solution which can be widely used by the industry and accepted as standard for designing of application specific chips.
The major adoption of RSIC-V architecture is in following sectors:
i) Automotive sector
ii) Wearable smart devices
iii) Smart mobile Phones
iv) IoT devices i.e. (Smart Home appliances, Industrial IoT devices, etc.).
v) Aerospace & Defence
vi) Data Centers
RISC-V is redefining the computing world by encouraging collaboration and innovation. RISC-V is emerging as disruptive technology. Technology is widely adopted by original equipment manufacturers like Apple, Samsung, Qualcomm, etc.
Recently, many domestic automotive companies have chosen RISC-V to build their own application specific MCUs, such as Wuhan BinarySemi, NationalChip, LinkedSemi, and ChipEXT.
NationalChip is exploring the possibilities in the high-end MCU chips for automotive electronics. News Link
Big Automotive chipset manufacturers Infineon, Nordic Semiconductor, NXP Semiconductors, Qualcomm, and Robert Bosch had invested in a new venture with the goal of advancing global adoption of RISC-V. Venture will act as a fuel for promotion and commercialization of products based on RISC-V architecture. News Link
Apple has announced designing of various all embedded systems using RISC-V. News Link
Amazon and Alibaba are using RISC-V for designing of their own data center processors/chips.
Google has planned to implement RISC-V for its AI silicon — TPU. News Link
Mindgrove debuts India’s first indigenous high-performance MCU chip. News Link